Workshop on Worldwide Opportunity in VLSI: From Campus to Industry
Organized by: Experts of Ulkasemi Pvt. Ltd.
Due to unavoidable circumstances, the deadline for paying for the workshop has been extended till 2nd January 2019.
Founded in 2007, Ulkasemi, an advanced semiconductor design and IP/Licensing company that offers customers flexible product development solutions from standard ASIC design to complete turnkey and derivative design. Company headquarters are located in Silicon Valley, California and Dhaka, Bangladesh. Our flexible model allows us to take projects as turnkey or on consulting basis. Ulkasemi assists its clients in developing their next generation flagship product lines e.g., mobile devices, complex routers/switches, consumer products, storage devices, microprocessors, graphics processors etc. at the cutting edge technologies that are key and rare in the industry. Today, Ulkasemi is Bangladesh’s Number 1 Semiconductor Design Service Company. After almost 12 years of offering professional Semiconductor Design and Front-End Verification Services, Ulkasemi has over 100 employees distributed around the globe and is aggressively growing.
Our sessions are devised in a way where the individual participant will be exposed to different steps in the complex yet fascinating design processes involved in the realization of a VLSI project from end-to-end. We want our audience to experience the contours of VLSI design in an era of accelerated innovation and constrained resources.
We want the participants to explore the indentations and in particular, with the massive opportunities which are arising out of the advancements in the field of VLSI, get familiar with the peripherals. We design systems and architectures and our focus at the workshop is thematically designed around four design parameters:
- Digital Front-End Verification
- Circuit Design
- Place and Route
Once completed, the individual participant will feel more confident about both the market opportunities and his/her capabilities for taking part in this grand adventure.
Session 1: Introduction to Digital Front-End Verification Flow
Presenter: Farshad, Member of Technical Staff (MTS)
Digital Front-End Verification checks the functional equivalency of the RTL code with the design specification and also checks for the functional correctness of RTL.The Front-End verification also ensures that all the functional features are tested and all parts of the RTL code is reached by the verification path by using a metric known as functional coverage and code coverage respectively.
Session 2: Introduction to Place and Route (PnR)
Presenter: Shafaitul Islam Surush, Senior Engineer
Physical design process is often referred as PnR (Place and Route) / APR (Automatic Place & Route). The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production. The physical design is the process of transforming a circuit description into the physical layout. Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Furthermore, design is often optimized w.r.t area, power and performance.
Session 3: Introduction to Circuit Design & Simulation
Presenter: S M Mojahidul Ahsan, Engineer.
The purpose of circuit design is to develop a circuit representation based on active and passive elements from design specifications. The transfer functions are converted into a circuit representation by taking into consideration the speed and power requirements of the original design. Circuit Simulation is used to verify the correctness and timing of each design component. Deep understanding of design hierarchy and circuit debugging ability are also crucial skills for a circuit designer.
Session 4: Custom IC Mask Design
Presenter: Wasif Absar, Assistant Engr.
Integrated circuit layout also known as IC layout design is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.
Outcome of the Workshop
- The participants will get the knowledge of different steps of Custom IC Design
- A workshop completion certificate will be provided to attending participants
No. of Participants
- The total number of participants is limited to 60
Last Date of Registration
20 December, 20182 January, 2019 (Final Extension)
Participants to which seminar is addressed
- 3rd and 4th year EEE Engineering Students
- Faculty members of EEE Engineering Department of Universities
Workshop Date, Time, Venue
- Date: 10 January, 2019 (Thursday)
- Time: 8:30 am – 5:30 pm
- Venue: It will be held in the premises of AIUB campus at Kuratoli Road, Kuril, Bangladesh,
Additional information on AIUB campus is available at the website www.aiub.edu
|Local participants||BDT 1000|
|Foreign participants||US$ 50|
*** Registration fee includes kit, handouts, lunch and refreshments.
For Registration, please click here
To download Flyer, please click here
Tentative Workshop Schedule
Date : January 10, 2019 (Thursday)
Time : 8:30 am to 5:30 pm
Venue : It will be held in the premises of AIUB campus at Kuratoli Road, Kuril, Dhaka
|8:15 am||:||Participants take their seats|
|8:30 am||:||Welcome Message by Prof. Dr. ABM Siddique Hossain, Dean, Faculty of Engineering|
|8:45 am||:||Session 1: Introduction to Digital Front-End Verification Flow by Farshad, Member of Technical Staff (MTS)|
|10:15 am||:||Snacks and Tea Break|
|10:30 am||:||Session 2: Introduction to Place and Route (PnR) by Shafaitul Islam Surush, Senior Engineer|
|12:00 pm||:||Lunch and prayer Break|
|1:00 pm||:||Session 3: Introduction to Circuit Design & Simulation by S M Mojahidul Ahsan, Engineer.|
|2:30 pm||:||Session 4: Custom IC Mask Design by Wasif Absar, Assistant Engr.|
|5:00 pm||:||Certificate Distribution by Professor Dr. ABM Siddique Hossain, Dean, Faculty of Engineering, AIUB|
|5:15 pm||:||Vote of thanks by Professor Dr. Md. Abdur Rahman, Assoc. Dean, Faculty of Engineering|